| 引用本文： |
-
张弘毅,王伟,林璟锵,华佳烽,马浩诚.硬件辅助安全技术研究综述[J].信息安全学报,已采用 [点击复制]
- ZhangHongyi,WangWei,LinJingqiang,HuaJiafeng,MaHaocheng.A Survey of Hardware-Assisted Security Technologies[J].Journal of Cyber Security,Accept [点击复制]
|
|
| 摘要: |
| 随着计算机系统复杂度的提高和攻击技术的快速演进，传统单纯依赖软件层的安全防御机制在安全强度与性能开销上已逐渐面临瓶颈，难以满足现代高安全等级的需求。在此背景下，硬件辅助安全实现作为一种将核心安全能力移至底层硬件实现的设计理念，由于其在安全性和性能等方面的显著优势，近年来在学术研究和工程实践中获得了广泛关注。此类方案通常以硬件内置的功能或机制为基础，辅助增强面向特定应用场景的安全防护能力，从而更为有效地缓解来自软硬件层的各种安全威胁。本文首先对主流硬件安全特性与相关辅助特性进行了深度梳理和系统阐述，主要包括两方面内容：一是介绍了主流处理器架构（如x86、ARM、RISC-V）提供的基本特性和陆续引入的扩展特性；二是深入解析了典型安全协处理器的架构特性和基本功能。在此基础上，本文进一步聚焦这些硬件特性在典型场景下的实际应用价值，依据近些年来的学术研究和工程应用，较为全面地总结了基于硬件特性构建安全屏障的设计思路与方案。针对安全机制并非绝不可破这一现实，本文亦探讨了硬件辅助安全技术面临的挑战，从底层物理、微架构以及上层软件三个攻击面梳理了潜在的攻击路径和利用技术。最后，结合当前计算机软硬件发展趋势，展望了硬件安全特性和其辅助安全实现的未来发展方向。 |
| 关键词: 硬件辅助安全 硬件特性 系统安全 处理器架构 可信执行环境 |
| DOI： |
| 投稿时间：2025-12-29修订日期：2026-07-21 |
| 基金项目:国家自然科学基金项目（面上项目，重点项目，重大项目） |
|
| A Survey of Hardware-Assisted Security Technologies |
|
ZhangHongyi1, WangWei1, LinJingqiang1, HuaJiafeng2, MaHaocheng2
|
| (1.School of Cyber Science and Technology, University of Science and Technology of China;2.Huawei Technologies) |
| Abstract: |
| With the increasing complexity of computer systems and the rapid evolution of attack techniques, traditional security defense mechanisms that rely solely on software layers are gradually encountering bottlenecks in both security strength and performance overhead, making it difficult to satisfy the requirements of modern systems with high security assurance. Against this background, hardware-assisted security, as a design paradigm that shifts core security capabilities to the underlying hardware, has attracted widespread attention in recent years due to its significant advantages in security and performance, in both academic research and engineering practice. Such approaches are typically built upon functionalities or mechanisms natively provided by hardware and aim to enhance security protection for specific application scenarios. By leveraging hardware-level support, these solutions can more effectively mitigate a wide range of security threats originating from both software and hardware layers. This paper first conducts a comprehensive review and systematic analysis of mainstream hardware security features and related auxiliary mechanisms, focusing on two main aspects. First, it introduces the fundamental features provided by mainstream processor architectures, such as x86, ARM, and RISC-V, as well as the architectural extensions that have been gradually introduced. Second, it presents an in-depth analysis of the architectural characteristics and basic functionalities of representative security coprocessors. Building on this foundation, the paper further focuses on the practical application value of these hardware features in typical scenarios. Based on academic research and engineering practices in recent years, it provides a relatively comprehensive summary of design ideas and representative solutions for constructing security barriers using hardware features. Considering the reality that security mechanisms are not absolutely unbreakable, the paper also discusses the challenges faced by hardware-assisted security technologies, outlining potential attack paths and exploitation techniques from three attack surfaces: the physical layer, the microarchitectural layer, and the upper software layer. Finally, in conjunction with current trends in the development of computer hardware and software, the paper looks ahead to future directions for the evolution of hardware security features and hardware-assisted security implementations. |
| Key words: Hardware-Assisted Security Hardware Features System Security Processor Architectures Trusted Execution Environment |
